Lam Research: Deposition and Etch Intensity Rising with More Complex Chips

TSMC’s Q2 earnings report and our 3nm thematic both came to the same conclusion: advanced packaging and advanced node capacity is increasingly overwhelmed, and the primary method to find relief comes down to new cleanroom space, or more WFE spending. TSMC boosted its 2026 capex by $8 billion in Q2 to $62 billion, with Lam positioned downstream as a key WFE beneficiary.

Lam’s earnings calls in Q3 and Q4 have highlighted one major upcoming growth driver lying within one of its smaller segments, NAND. Back in Q3, management noted that their previously-forecast $40 billion in NAND equipment spending is now arriving at an accelerated rate as data center bit mix increases, creating dual tailwinds for growth via tool upgrades and new greenfield builds: “We said in early 2025 that roughly $40 billion in conversion spending would be required over several years to enable existing NAND installed wafer capacity to produce devices with more than 200 layers. We now anticipate that this conversion will be pulled forward with the majority of spending occurring before the end of calendar year 2027.”

One of Q4’s key reveals leaned into that $40 billion figure and Lam’s served addressable market (SAM) in NAND, as the upgrade cycle from 200-layer to 300-layer and eventually 500-layer NAND could double Lam’s NAND SAM per wafer on a larger installed base (hinting that the $40 billion upgrade cycle will get even larger).

However, NAND is not expected to be the growth driver for Lam in 2027, with management placing it as the third fastest next year, following DRAM and Foundry. More on this below.