ounce-mp.dts
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| /dts-v1/; | |
| / { | |
| nintendo,buildrevision = "f7aea707909d02195e61ea649b0d9637a354fca2"; | |
| nintendo,buildrevisiondate = "2024-06-06T08:07:35Z"; | |
| compatible = "nintendo,ounce-mp", "nintendo,ounce"; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| interrupt-parent = <0x1>; | |
| model = "Nintendo Ounce, MP"; | |
| chosen { | |
| nintendo,bootmode = "normal"; | |
| }; | |
| interrupt-controller@f400000 { | |
| compatible = "arm,cortex-a15-gic"; | |
| #interrupt-cells = <0x3>; | |
| interrupt-controller; | |
| reg = <0x0 0xf400000 0x0 0x1000 0x0 0xf410000 0x0 0x1000 0x0 0xf420000 0x0 0x1000 0x0 0xf430000 0x0 0x1000>; | |
| interrupt-parent = <0x1>; | |
| status = "disabled"; | |
| phandle = <0x1>; | |
| }; | |
| pinmux@2430000 { | |
| compatible = "nvidia,tegra239-pinmux"; | |
| reg = <0x0 0x2430000 0x0 0x1000>; | |
| init-pins { | |
| extperiph1_clk_pc2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x8>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| extperiph2_clk_pc3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x0>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| cam_i2c_scl_pc4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x18>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| pull-down-strength = <0x1f>; | |
| }; | |
| cam_i2c_sda_pc5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x10>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| pull-down-strength = <0x1f>; | |
| }; | |
| soc_gpio23_pc6 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x20>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio24_pc7 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x28>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio27_pd0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x40>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x1>; | |
| }; | |
| soc_gpio55_pd1 { | |
| pull = <0x1>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x90>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio29_pd2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x50>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio33_pd3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x70>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio32_pd4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x68>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio35_pd5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x78>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio37_pd6 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x80>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio56_pd7 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x88>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| uart1_tx_pe0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0xb0>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| uart1_rx_pe1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0xa8>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| uart1_rts_pe2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0xa0>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| uart1_cts_pe3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x98>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| }; | |
| }; | |
| pinmux@2432000 { | |
| compatible = "nvidia,tegra239-pinmux"; | |
| reg = <0x0 0x2432000 0x0 0x1000>; | |
| init-pins { | |
| soc_gpio167_pp0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x40>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio168_pp1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x48>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio169_pp2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x50>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio170_pp3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x58>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| dap4_sclk_pp4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x0>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| dap4_dout_pp5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x8>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| dap4_din_pp6 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x10>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| dap4_fs_pp7 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x18>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio171_pq0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x60>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio172_pq1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x68>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio173_pq2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x70>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| }; | |
| }; | |
| pinmux@2434000 { | |
| compatible = "nvidia,tegra239-pinmux"; | |
| reg = <0x0 0x2434000 0x0 0x1000>; | |
| init-pins { | |
| soc_gpio13_pf0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x50>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| soc_gpio14_pf1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x58>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio15_pf2 { | |
| pull = <0x2>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x60>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio16_pf3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x68>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio17_pf4 { | |
| pull = <0x2>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x70>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio18_pf5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x78>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio20_pf6 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x38>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio21_pf7 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x40>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio22_pg0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x48>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio06_pg1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0xa8>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| uart4_tx_pg2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x20>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| uart4_rx_pg3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x18>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| uart4_rts_pg4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x10>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| uart4_cts_pg5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x8>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio41_pg6 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x88>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio42_pg7 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x90>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio43_ph0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x98>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio44_ph1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0xa0>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| gen1_i2c_scl_ph2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x28>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| gen1_i2c_sda_ph3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x30>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| soc_gpio07_ph5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0xb0>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| }; | |
| }; | |
| pinmux@2437000 { | |
| compatible = "nvidia,tegra239-pinmux"; | |
| reg = <0x0 0x2437000 0x0 0x1000>; | |
| init-pins { | |
| pex_l0_clkreq_n_pw0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x20>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| pex_l0_rst_n_pw1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x28>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| pex_l1_clkreq_n_pw2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x10>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| pex_l1_rst_n_pw3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x18>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| pex_l2_clkreq_n_pw4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x0>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| pex_l2_rst_n_pw5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x30>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| pex_l3_clkreq_n_pw6 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x38>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| pex_l3_rst_n_pw7 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x40>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| pex_wake_n_px0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x8>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| dp_aux_ch0_hpd_px1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x48>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| }; | |
| }; | |
| pinmux@2438000 { | |
| compatible = "nvidia,tegra239-pinmux"; | |
| reg = <0x0 0x2438000 0x0 0x1000>; | |
| init-pins { | |
| sdmmc1_clk_pu0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x0>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| sdmmc1_cmd_pu1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x8>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| sdmmc1_dat0_pu2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x30>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| sdmmc1_dat1_pu3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x28>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| sdmmc1_dat2_pu4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x20>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| sdmmc1_dat3_pu5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x18>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| }; | |
| }; | |
| pinmux@243b000 { | |
| compatible = "nvidia,tegra239-pinmux"; | |
| reg = <0x0 0x243b000 0x0 0x1000>; | |
| init-pins { | |
| qspi0_sck_pl0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x10>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| qspi0_io0_pl1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x0>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| qspi0_io1_pl2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x8>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| qspi0_cs_n_pl3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x18>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio152_pl4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x40>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio153_pl5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x48>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio154_pl6 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x38>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio155_pl7 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x28>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio156_pm0 { | |
| pull = <0x1>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x20>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio157_pm1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x68>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio158_pm2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x70>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio159_pm3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x60>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio160_pm4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x30>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio161_pm5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x50>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio162_pm6 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x58>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| uart7_tx_pm7 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x88>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| uart7_rx_pn0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x90>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| uart7_rts_pn1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x80>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| uart7_cts_pn2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x78>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| }; | |
| }; | |
| pinmux@c301000 { | |
| compatible = "nvidia,tegra239-pinmux"; | |
| reg = <0x0 0xc301000 0x0 0x1000>; | |
| init-pins { | |
| ao_bootv_ctl_n_paa0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x28>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_soc_gpio00_paa1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0xf0>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_vcomp_alert_paa2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x58>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_pwm1_paa3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x1c0>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_batt_oc_paa4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x20>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_soc_gpio04_paa5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x140>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_soc_gpio25_paa6 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x158>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_soc_gpio26_paa7 { | |
| pull = <0x2>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x160>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_hdmi_cec_pbb0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x60>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_spi2_sck_pcc0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0xb0>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_spi2_miso_pcc1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0xb8>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_spi2_mosi_pcc2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x90>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_spi2_cs0_pcc3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0xa0>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_spi2_cs1_pcc4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x1c8>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_uart3_tx_pcc5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x78>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_uart3_rx_pcc6 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x70>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_gen2_i2c_scl_pcc7 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x98>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| pull-down-strength = <0x1f>; | |
| }; | |
| ao_gen2_i2c_sda_pdd0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0xa8>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| pull-down-strength = <0x1f>; | |
| }; | |
| ao_gen8_i2c_scl_pdd1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x88>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| pull-down-strength = <0x1f>; | |
| }; | |
| ao_gen8_i2c_sda_pdd2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x80>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| pull-down-strength = <0x1f>; | |
| }; | |
| ao_touch_clk_pdd3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x68>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_dmic1_clk_pdd4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x1d0>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_dmic1_dat_pdd5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x1d8>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_soc_gpio19_pdd6 { | |
| pull = <0x2>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0xf8>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_pwm2_pdd7 { | |
| pull = <0x2>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x1b0>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_pwm3_pee0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x1b8>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_pwm7_pee1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x1a8>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_soc_gpio49_pee2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0xc0>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_soc_gpio82_pee3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0xd0>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_soc_gpio50_pee4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0xc8>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_soc_gpio83_pee5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x128>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_soc_gpio69_pff0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x150>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_soc_gpio70_pff1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x138>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_soc_gpio71_pff2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0xd8>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_soc_gpio72_pff3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x108>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_soc_gpio73_pff4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x130>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_soc_gpio74_pff5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0xe8>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_soc_gpio80_pff6 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x118>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_soc_gpio76_pff7 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0xe0>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_soc_gpio77_pgg0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x110>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_soc_gpio84_pgg1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x120>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| ao_uart2_tx_pgg2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x178>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_uart2_rx_pgg3 { | |
| pull = <0x2>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x180>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_uart2_rts_pgg4 { | |
| pull = <0x1>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x190>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_uart2_cts_pgg5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x188>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_soc_gpio85_pgg6 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x148>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_uart5_tx_pgg7 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x168>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_uart5_rx_phh0 { | |
| pull = <0x2>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x170>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_uart5_rts_phh1 { | |
| pull = <0x1>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x1a0>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_uart5_cts_phh2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x198>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| ao_soc_gpio86_phh3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x100>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| }; | |
| }; | |
| pinmux@243d000 { | |
| compatible = "nvidia,tegra239-pinmux"; | |
| reg = <0x0 0x243d000 0x0 0x1000>; | |
| init-pins { | |
| gpu_pwr_req_pa0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x50>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| gp_pwm5_pa1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x58>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| gp_pwm6_pa2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x60>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| spi3_sck_pa3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x30>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| spi3_miso_pa4 { | |
| pull = <0x1>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x0>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| spi3_mosi_pa5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x48>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| spi3_cs0_pa6 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x10>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| spi3_cs1_pa7 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x20>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| spi1_sck_pb0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x28>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| spi1_miso_pb1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x18>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| spi1_mosi_pb2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x40>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| spi1_cs0_pb3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x8>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| spi1_cs1_pb4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x38>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| }; | |
| }; | |
| pinmux@2440000 { | |
| compatible = "nvidia,tegra239-pinmux"; | |
| reg = <0x0 0x2440000 0x0 0x1000>; | |
| init-pins { | |
| gen4_i2c_scl_ps0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0xb8>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| pull-down-strength = <0x1f>; | |
| }; | |
| gen4_i2c_sda_ps1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0xb0>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| pull-down-strength = <0x1f>; | |
| }; | |
| soc_gpio75_ps2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x30>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x1>; | |
| }; | |
| gen7_i2c_scl_ps3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0xa0>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| pull-down-strength = <0x1f>; | |
| }; | |
| gen7_i2c_sda_ps4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0xa8>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| pull-down-strength = <0x1f>; | |
| }; | |
| soc_gpio78_ps5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x40>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| gen9_i2c_scl_ps6 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0xc8>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| gen9_i2c_sda_ps7 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0xc0>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| soc_gpio81_pt0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x38>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| soc_gpio36_pt1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x0>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio53_pt2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x8>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio38_pt3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x18>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio40_pt4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x28>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio34_pt5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x48>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| usb_vbus_en0_pt6 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0xd0>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| usb_vbus_en1_pt7 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0xd8>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| io-hv = <0x0>; | |
| }; | |
| }; | |
| }; | |
| pinmux@2441000 { | |
| compatible = "nvidia,tegra239-pinmux"; | |
| reg = <0x0 0x2441000 0x0 0x1000>; | |
| init-pins { | |
| ufs0_ref_clk_pv0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x8>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| ufs0_rst_n_pv1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x0>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| }; | |
| }; | |
| pinmux@2448000 { | |
| compatible = "nvidia,tegra239-pinmux"; | |
| reg = <0x0 0x2448000 0x0 0x1000>; | |
| init-pins { | |
| dap3_clk_pj0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x68>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| dap3_dout_pj1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x78>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| dap3_din_pj2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x70>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| dap3_fs_pj3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x60>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio57_pj4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x20>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio58_pj5 { | |
| pull = <0x2>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x28>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio59_pj6 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x30>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio60_pj7 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x38>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio45_pk0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x0>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio46_pk1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x8>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio47_pk2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x10>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio48_pk3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x18>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| }; | |
| }; | |
| pinmux@244f000 { | |
| compatible = "nvidia,tegra239-pinmux"; | |
| reg = <0x0 0x244f000 0x0 0x1000>; | |
| init-pins { | |
| soc_gpio61_pr0 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x1>; | |
| reg-ofs = <0x0>; | |
| tristate = <0x0>; | |
| enable-input = <0x1>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio62_pr1 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x8>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio63_pr2 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x10>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio64_pr3 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x18>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio65_pr4 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x20>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio66_pr5 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x28>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio67_pr6 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x30>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| soc_gpio68_pr7 { | |
| pull = <0x0>; | |
| gpio-sf-sel = <0x0>; | |
| reg-ofs = <0x38>; | |
| tristate = <0x0>; | |
| enable-input = <0x0>; | |
| schmitt = <0x0>; | |
| }; | |
| }; | |
| }; | |
| gpio@2200000 { | |
| compatible = "nvidia,tegra239-gpio"; | |
| reg-names = "security", "gpio"; | |
| reg = <0x0 0x2200000 0x0 0x4000 0x0 0x2210000 0x0 0x4000>; | |
| interrupts = <0x0 0x124 0x4 0x0 0x12c 0x4 0x0 0x134 0x4 0x0 0x13c 0x4>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| status = "disabled"; | |
| #nintendo,devicecode-cells = <0x3>; | |
| gpio-pads { | |
| nintendo,devicecode = <0x39000097 0x0 0x1 0x3d000001 0x2 0x2 0x100040b 0x7 0x1 0x100040c 0xc 0x1 0x39000466 0x12 0x1 0xc9000403 0x16 0x0 0x100040d 0x17 0x1 0x4000401 0x18 0x2 0x35000036 0x19 0x0 0x100040e 0x1b 0x1 0x100040f 0x1c 0x1 0x34000033 0x1d 0x1 0x1000410 0x1e 0x1 0x3a000409 0x1f 0x4 0x1000429 0x20 0x1 0x33000404 0x21 0x1 0x1000412 0x22 0x1 0x1000413 0x23 0x1 0x35000002 0x28 0x0 0x1000414 0x29 0x1 0x33000003 0x2a 0x0 0xc9000402 0x2b 0x0 0x35000003 0x2c 0x0 0x33000004 0x2d 0x0 0x3c000002 0x2e 0x0 0x3c000403 0x2f 0x1 0x3c000402 0x30 0x1 0x33000401 0x31 0x1 0x1000415 0x32 0x1 0x1000416 0x33 0x1 0x1000417 0x34 0x1 0x1000418 0x35 0x1 0x3c000407 0x36 0x1 0x100041a 0x37 0x1 0x100041b 0x38 0x1 0x100041c 0x39 0x1 0x100041d 0x3a 0x1 0x100041e 0x3b 0x1 0x3c000405 0x3d 0x0 0x100041f 0x44 0x1 0x3c000406 0x45 0x0 0x37000402 0x47 0x2 0x1000421 0x48 0x1 0x1000422 0x49 0x1 0x1000423 0x4a 0x1 0x1000424 0x4b 0x1 0x1000425 0x50 0x1 0x1000426 0x51 0x1 0x1000427 0x52 0x1 0x1000428 0x53 0x1 0x37000401 0x54 0x0 0x4000404 0x55 0x0 0x4000403 0x56 0x1 0x40000cd 0x57 0x2 0x34000402 0x58 0x0 0x3c000465 0x59 0x1 0x39000467 0x5a 0x2 0x39000465 0x5b 0x1 0x3c000401 0x5c 0x1 0x34000035 0x5d 0x1 0x34000034 0x5e 0x1 0x100042a 0x5f 0x1 0x100042b 0x60 0x1 0x100042c 0x61 0x1 0x100042d 0x62 0x1 0x3c000466 0x68 0x1 0x100042e 0x69 0x1 0x100042f 0x6a 0x1 0x1000430 0x6b 0x1 0x1000431 0x70 0x1 0x1000432 0x71 0x1 0x1000433 0x72 0x1 0x3a000402 0x78 0x0 0x38000002 0x79 0x2 0x1000447 0x7a 0x1 0x3400003e 0x7b 0x1 0x1000434 0x7c 0x1 0x1000435 0x7d 0x1 0x1000436 0x7e 0x1 0x1000437 0x7f 0x1 0x4000402 0x82 0x0 0x1000438 0x85 0x1 0x1000439 0x86 0x1 0x100043a 0x87 0x1 0x100043b 0x88 0x1 0x100043c 0x89 0x1 0x100043d 0x8a 0x1 0x100043e 0x8b 0x1 0x100043f 0x8c 0x1 0x1000440 0x8d 0x1 0x1000441 0x8e 0x1 0x1000442 0x8f 0x1 0x1000443 0xa0 0x1 0x1000444 0xa1 0x1 0x38000403 0xa2 0x1 0x38000404 0xa3 0x1 0xca000400 0xa4 0x0 0x1000445 0xa6 0x1 0x1000446 0xa7 0x1 0x38000004 0xa8 0x0>; | |
| }; | |
| }; | |
| gpio@c2f0000 { | |
| compatible = "nvidia,tegra239-gpio-aon"; | |
| reg-names = "security", "gpio"; | |
| reg = <0x0 0xc2f0000 0x0 0x1000 0x0 0xc2f1000 0x0 0x1000>; | |
| interrupts = <0x0 0x38 0x4>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| status = "disabled"; | |
| #nintendo,devicecode-cells = <0x3>; | |
| gpio-pads { | |
| nintendo,devicecode = <0x3a000404 0x0 0x4 0x3e000002 0x1 0x0 0x39000004 0x2 0x0 0x35000401 0x3 0x1 0x1000401 0x4 0x1 0x3500040b 0x5 0x1 0x39000002 0x6 0x0 0x3a000403 0x7 0x0 0x1000402 0x8 0x1 0x1000403 0x14 0x1 0x1000404 0x1b 0x1 0x1000405 0x1c 0x1 0x1000406 0x1d 0x1 0x3a000401 0x1e 0x0 0x35000040 0x1f 0x0 0x1000407 0x20 0x1 0x1000408 0x21 0x1 0x3c000404 0x22 0x0 0x39000034 0x23 0x0 0x37000004 0x24 0x0 0x38000402 0x25 0x1 0x40000cb 0x28 0x0 0x40000ca 0x2e 0x1 0x100044a 0x2f 0x1 0x39000469 0x30 0x1 0x39000468 0x31 0x1 0x35000402 0x32 0x1 0x35000403 0x33 0x0 0x35000404 0x34 0x0 0x35000405 0x35 0x1 0x37000002 0x36 0x2 0x3500040c 0x37 0x1 0x3500040d 0x38 0x0 0x3500040e 0x39 0x0 0x3500040f 0x3a 0x1 0x38000401 0x3b 0x2>; | |
| }; | |
| }; | |
| i2c@3160000 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "nvidia,tegra239-i2c"; | |
| reg = <0x0 0x3160000 0x0 0x100>; | |
| interrupts = <0x0 0x19 0x4>; | |
| clock-frequency = <0x61a80>; | |
| nintendo,devicecode = <0x2000001>; | |
| status = "disabled"; | |
| }; | |
| i2c@c240000 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "nvidia,tegra239-i2c"; | |
| reg = <0x0 0xc240000 0x0 0x100>; | |
| interrupts = <0x0 0x1a 0x4>; | |
| clock-frequency = <0x186a0>; | |
| nintendo,devicecode = <0x2000002>; | |
| extcon@51 { | |
| nintendo,devicecode = <0x35000415>; | |
| reg = <0x51>; | |
| }; | |
| extcon-inspection@50 { | |
| nintendo,devicecode = <0x35000465>; | |
| reg = <0x50>; | |
| }; | |
| }; | |
| i2c@3180000 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "nvidia,tegra239-i2c"; | |
| reg = <0x0 0x3180000 0x0 0x100>; | |
| interrupts = <0x0 0x1b 0x4>; | |
| clock-frequency = <0x61a80>; | |
| nintendo,devicecode = <0x2000003>; | |
| ucsi_ccg@8 { | |
| nintendo,devicecode = <0x40000c9>; | |
| reg = <0x8>; | |
| }; | |
| }; | |
| i2c@3190000 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "nvidia,tegra239-i2c"; | |
| reg = <0x0 0x3190000 0x0 0x100>; | |
| interrupts = <0x0 0x1c 0x4>; | |
| clock-frequency = <0x186a0>; | |
| nintendo,devicecode = <0x2000004>; | |
| max77986@6b { | |
| compatible = "maxim,max77986"; | |
| nintendo,devicecode = <0x39000001>; | |
| reg = <0x6b>; | |
| }; | |
| }; | |
| i2c@31a0000 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "nvidia,tegra239-i2c"; | |
| reg = <0x0 0x31a0000 0x0 0x100>; | |
| interrupts = <0x0 0x1d 0x4>; | |
| clock-frequency = <0x61a80>; | |
| nintendo,devicecode = <0x2000005>; | |
| nintendo,driver = "bpmpmrq"; | |
参与讨论