The EDA Crash & The Massive AI Opportunity

Introduction - the Chip Design Flow

We’ve written extensively on EDA (electronic design automation) software in the past. For newcomers on the topic, a recent expert call with a VP at Analog Devices gave a good overview of the space:

“EDA varies if you’re doing digital or analog design. Let me start with digital because that’s where a lot of companies are focused. In doing digital design, you start with a specification of what you want to build. That specification is normally in some form of natural language. That specification is then converted into the front-end logic design, where engineers use the different logic components to implement that design. After this design phase is the RTL generation phase. RTL is actually the code to implement the design—this can be in something like Verilog (a hardware description language used to model electronic systems). That RTL then goes through a verification step. Essentially, we test that logic to make sure it’s working properly. After that phase is complete, the back-end or physical design phase happens, where you physically map the logic design to the chip area that you want to implement. Once the physical design is complete, another round of testing is done to make sure all the logic, all the timing is all still working.Only after that final phase of testing the physical design is the design ready for tape-out in manufacturing. Those are the high-level steps to build a microcontroller or some form of digital design. Most semiconductor companies will leverage a lot of software tools to help them through these different phases. The two most common partners to work with on this whole workflow are companies like Cadence and Synopsys, and Siemens as a third. They make this much easier by providing an integrated workflow to accomplish these different phases.We use both companies. Cadence we leverage for a lot of our analog design and Synopsys for a lot of digital design. We’re leveraging their flows pretty much end-to-end—all…