Altera and Riverlane Validate QECi on Agilex FPGAs – and the Day After, Qblox Closes the Real-Time QEC Loop at 6.9 µs

Correction, September 25, 2026: An earlier version of this article gave the Project SKYTALE grant as €2.5 million; Riverlane’s award is £2.1 million. It also described the QECi specification as open source; the QECIPHY physical layer is open source, and the specification is distributed under license. A reference to my decoder analysis, which does not cover QECi or NVQLink, has been removed, and several descriptions were made more precise.

September 10, 2026 – FPGA manufacturer Altera and quantum error correction specialist Riverlane announced a partnership to validate Riverlane’s Quantum Error Correction Interface (QECi) protocol on Altera’s Agilex 7 FPGAs. Riverlane has published the open-source QECi design example on GitHub, including the physical-layer implementation for Agilex F-Tile transceivers. Riverlane also joined the Altera Solutions Acceleration Partner Program.

QECi is a standardized interface specification that defines the data format, runtime states, and communication protocol between quantum control electronics and quantum error correction hardware. The protocol is designed to allow developers to pair different control systems and decoders without bespoke integration for each combination.

Riverlane built the design example on the Agilex 7’s F-Tile high-speed transceivers, which carry data between the quantum control system and the decoder hardware. Altera says Agilex FPGAs give QECi the deterministic low latency required for real-time error correction. The partnership also covers the broader Agilex portfolio, including the Direct RF FPGAs in the Agilex 9 family, with integrated data converters operating at up to 64 billion samples per second across a 36 GHz RF range.

Altera, which operated as Intel’s Programmable Solutions Group from 2015 and has been majority-owned by Silver Lake since September 2025, rates Agilex 7 at twice the performance per watt of competing 7 nm FPGAs.

The QEC partnership followed two days after Altera’s September 8 announcement that it had added native post-quantum cryptography support to two device families, the entry-level Agilex 3 and the mid-range Agilex 5. That PQC capability – secure boot, built into the hardware via the Secure Device Manager, which also handles bitstream encryption, key management, and platform attestation – targets long-life defense, industrial, and edge infrastructure.

One day after the Altera announcement, on September 11, control electronics maker Qblox and Riverlane published results from a full real-time QEC feedback loop running over QECi as part of Project SKYTALE, a Horizon Europe EIC Transition project backed by a £2.1 million grant. Using emulated qubit measurement data on physical Qblox Cluster hardware connected to Riverlane’s Deltaflow 2 system, they demonstrated total round-trip latency – from syndrome extraction to conditional correction, including readout integration time – of 6.886 µs at code distance 3 (Surface-17, 17 physical qubits) and 11.886 µs at code distance 9 (Surface-161, 161 physical qubits). All configurations fell within the 20 µs near-term round-trip latency target Riverlane has published. Qblox’s own contribution to round-trip latency increased by only 106 nanoseconds – from 1.114 µs to 1.220 µs – across that nearly tenfold increase in qubit count.

My Analysis

What Riverlane is building with QECi

It is easy to read the partnership as an FPGA vendor validating an open-source reference design. Riverlane already has a decoder in Deltaflow 2. What it is building now is control-electronics and FPGA vendor support for QECi, the interface specification that defines the link between any control system and any decoder.

The decoder performs the computation. The interface defines how syndrome data gets to the decoder, and how correction instructions get back. A surface-code round on superconducting hardware runs in roughly one microsecond, and the decoder must keep pace with that rate – the total feedback budget from syndrome extraction to correction is single-digit to low-tens of microseconds. The interface is where nanoseconds are spent or saved, and where the choice of transport protocol locks in or opens up the hardware options for everything downstream.

With the Altera validation, QECi now runs on hardware from three distinct layers of the quantum control stack. Qblox provides the control electronics. Altera provides the FPGA fabric. Riverlane provides the decoder. Each can be swapped independently. NVQLink has its own multi-vendor demonstrations – Quantinuum’s Helios result being the most prominent – but I know of no other QEC-specific interface with support from control, FPGA, and decoder vendors and a closed-loop demonstration.

QECi versus NVQLink

The control-to-decoder interface has become one of the critical specification decisions for any fault-tolerant quantum computing program.

NVIDIA’s NVQLink uses RDMA-over-Converged-Ethernet (RoCE), a general-purpose high-speed transport adapted for the QEC data path. It has the broadest vendor backing: NVIDIA’s GPU platform, Quantinuum’s demonstration of a 67 µs decoder reaction time for qLDPC codes on the Helios trapped-ion system, and integration with the CUDA-Q programming model.

Riverlane’s QECi takes a different approach. It is a protocol designed from scratch for the specific data patterns of syndrome decoding. Riverlane has argued, as reported by Quantum Computing Report, that RoCE-based interfaces may encounter bottlenecks beyond roughly 300 physical qubits, while QECi is engineered to maintain round-trip transport latency under 400 nanoseconds at higher qubit counts – that figure covers the interface protocol overhead only, exclusive of readout integration and decoder processing time.

The Qblox demonstration provides end-to-end data on QECi’s scaling behavior. At Surface-17, Qblox’s system contribution was 1.114 µs. At Surface-161 – a nearly tenfold increase in qubit count – it was 1.220 µs, a growth of 106 nanoseconds. The syndrome data rate at Surface-17 was 8 Mb/s, more than two orders of magnitude below the Qblox Cluster’s 2 Gb/s throughput ceiling. With that much headroom, decoder processing time is the bottleneck. Decoder-side improvements pass directly through to system-level gains, a property Qblox demonstrated when a Deltaflow 2 update reduced Surface-17 round-trip latency from 8.308 µs to 6.886 µs – a 17% improvement that appeared in the total latency without any change on the control side.

Neither approach has won. NVQLink has the advantage of vendor scale and GPU-accelerated decoding for longer-cycle-time architectures like trapped ions. QECi has the advantage of protocol specificity and demonstrated flat scaling in the control layer. For superconducting systems with their microsecond QEC cycles, where the latency budget is measured in single-digit microseconds rather than milliseconds, QECi’s purpose-built design may have a structural advantage. For any system where the decoder itself can tolerate millisecond-class latency – trapped ions, certain neutral-atom architectures – NVQLink’s general-purpose flexibility and GPU integration are compelling.

The procurement implication is the same either way: the control-to-decoder interface is a specification decision that must be made early and costs heavily to change later. Riverlane and NVIDIA have each published theirs. Buyers who defer the choice until they need fault tolerance will find that their control architecture was implicitly locked in by whatever transport their control vendor chose.

Altera’s two announcements and the supply chain

The back-to-back announcements from Altera are individually modest. Taken together, they put Altera on both sides of the quantum transition. On September 8, Altera announced PQC support in Agilex 3 and 5 devices to protect classical infrastructure against the quantum threat. On September 10, it announced QECi support on Agilex 7 and 9 for the control fabric of the quantum hardware that creates the threat.

The PQC migration and the fault-tolerant quantum computing build-out belong to the same transition. Altera ships silicon for both without having to predict when a CRQC will arrive.

For the supply chain, this means commercial FPGA vendors now treat quantum control as a production use case. Riverlane has joined Altera’s formal partner program and published a design example. Altera has committed Agilex 7 and 9 to the partnership. It means quantum hardware developers can specify Altera FPGAs in a bill of materials, point to a validated reference design, and tell their procurement team to buy parts through standard semiconductor distribution. That is different from a research collaboration.

Where the decoder bottleneck actually is

Riverlane’s LCD – the Local Clustering Decoder at the core of Deltaflow 2 – achieves sub-microsecond per-round decoding latency on FPGA hardware. The Nature Communications paper published in December 2025 confirmed this without a QPU, using a simulated superconducting circuit-level noise model with stochastic leakage and relaxation channels. That noise model is realistic enough to validate the decoder’s adaptive performance.

Separately, in April 2026, Riverlane replayed Google’s Willow distance-5 experimental readout data through its QPU and control system emulator over QECi. Deltaflow 2 demonstrated a mean end-to-end latency of 16.32 µs on that data – roughly four times faster than the 63 µs reported in Google’s original 2024 study, and a maximum sub-shot latency more than ten times better than Google’s. Riverlane itself cautions against a like-for-like reading, because latency was a secondary goal of Google’s paper and Riverlane counts the whole QEC system in its own figure. The Willow traces are real experimental data, but no QPU was connected during the replay. The Qblox demonstration has the same limitation.

Those are encouraging numbers, but they need context. The 16.32 µs mean latency covers the full system, including data routing, windowed decoding, and result delivery. Riverlane’s own target for utility-scale operation is approximately 10 µs. With 6.886 µs at distance 3 and 11.886 µs at distance 9, Qblox and Riverlane have moved the demonstrated state of the art closer to that threshold, but the test used emulated qubit measurement data with no QPU attached. A running QPU adds noise variability, calibration drift, and the nondeterministic latency spikes that real hardware produces.

The path from 6.9 µs on emulated data to sustained sub-10 µs on a real QPU at distance 7 or higher – the regime where surface-code error correction starts to deliver practical advantage – is the engineering gap between a demonstrated capability and a deployed one. Riverlane’s roadmap places Deltaflow 3, with streaming logic for continuous error-corrected operations, in late 2026 – slipped by approximately one year from the original 2024 roadmap, which targeted 2025. That release will be the test of whether the architecture transitions from a demonstrated interface to a production QEC stack.

Does this move the CRQC timeline?

Directly, no. The decoder is not the gating factor for when a cryptographically relevant quantum computer arrives. The physical qubit quality, the engineering of million-qubit systems, and the scale of fault-tolerant integration are earlier and harder constraints. My CRQC Quantum Capability Framework places decoder performance in the system-level execution tier as Capability D.2, which is maturing but depends on the physical-layer capabilities beneath it.

Riverlane, Altera, and Qblox have weakened one argument against fault-tolerant quantum computing: that real-time decoding at superconducting speeds is impractical with commercially available hardware. The QECi stack now has a standard interface, a sub-microsecond decoder, and a demonstrated full-loop latency under 7 µs at distance 3, all on commercial FPGA hardware and control electronics. The engineering gap between here and a CRQC is enormous. But the decoder is no longer the part of that gap where progress is stalled.

For organizations planning PQC migration, the announcement adds evidence that fault tolerance is advancing on engineering as well as physics. A standardized, validated QEC interface stack of control electronics, FPGA fabric and decoder is infrastructure, and the move from custom laboratory integrations to procurement-grade reference designs is one of the markers I track for when fault tolerance stops being a research program and starts being an engineering one.

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