Infleqtion and NVIDIA Build a qLDPC Compiler Pipeline, But the Code Has Not Yet Run on Hardware

September 14, 2026 – Infleqtion (NYSE: INFQ) announced the integration of its open-source quantum low-density parity-check (qLDPC) software library with NVIDIA CUDA-Q Logical, a new orchestration and compiler layer for logical qubits within NVIDIA’s CUDA-Q platform, at IEEE Quantum Week 2026 in Toronto on September 14, 2026.

Using an early-access version of CUDA-Q Logical, Infleqtion researchers constructed and validated a Hypergraph-Product Simplex (HGPS) quantum error correction code block with parameters [[98,18,4]] – 18 logical qubits encoded in 98 physical data qubits, a ratio of approximately 5.4 data qubits per logical qubit. The code was derived from a 7-bit cyclic classical simplex seed with [7,3,4] parameters and yielded an 18.4% encoding rate.

The code block contains 49 X-type and 49 Z-type checks, each of weight six, with canonical logical representatives of weight four. Infleqtion verified stabilizer commutativity over GF(2) and demonstrated multi-owner logical memory allocation by compiling a joint X-by-Z product measurement across two distinct logical qubit owners within a single HGPS block.

“The path to useful quantum computing depends on turning advances in error correction into full-stack architectures that can run on real hardware,” said Sam Stanwyck, Director of Quantum Product at NVIDIA. “Infleqtion’s integration of the qLDPC library with CUDA-Q Logical shows how researchers can design and evaluate logical qubit workloads end to end for their quantum processors.”

Infleqtion open-sourced the qLDPC library last year in collaboration with researchers from JPMorgan Chase. The construction builds on architecture research from the laboratory of Professor Fred Chong, Infleqtion’s Chief Scientist for Quantum Software, targeting reconfigurable neutral-atom arrays.

CUDA-Q Logical, also unveiled at IEEE Quantum Week, is a retargetable compilation framework that maps logical-qubit workloads onto the physical execution layer. According to NVIDIA, Fermilab researchers used CUDA-Q Logical to reduce fault-tolerant architecture development cycles from five months to three weeks – a sevenfold acceleration. The platform is designed to be hardware-agnostic: using CUDA-Q Logical, Iceberg Quantum mapped its Pinnacle architecture onto Diraq’s silicon-spin platform and confirmed that Diraq’s 1,000-logical-qubit target could be met with approximately 150,000 physical qubits – a figure NVIDIA describes as roughly ten times below Diraq’s previous estimates.

Infleqtion said it is extending the workflow toward physical execution on its neutral-atom hardware, with next steps including physical syndrome extraction schedules, atom-loss and leakage noise modelling, detector error model generation, and real-time GPU decoder benchmarking via the NVIDIA Ising model family.

At the same conference, Infleqtion’s Pranav Gokhale received the 2026 IEEE Quantum Technical Community Distinguished Early Career Award.

My Analysis

The headline number from Infleqtion’s announcement, 5.4 physical data qubits per logical qubit, is correct for the [[98,18,4]] code. In 2026, fault-tolerance roadmaps are judged credible or aspirational by their physical-to-logical ratio. But the number requires context that the press release does not foreground, and NVIDIA’s CUDA-Q Logical compiler layer may be a more significant development than the code itself.

The ratio in context

Infleqtion’s HGPS [[98,18,4]] code encodes 18 logical qubits into a block of 98 physical data qubits. That 5.4:1 data-qubit ratio is a real improvement over surface codes, which at distance 3 require 9 data qubits for a single logical qubit and at distance 5 require 25.

First, the 98 data qubits are not the full physical cost. The code’s 49 X-type and 49 Z-type checks each require ancilla qubits for syndrome measurement. Assuming one dedicated ancilla per check with no reuse – a standard assumption for CSS codes, though neutral-atom arrays may allow ancilla reuse across serial extraction rounds – the total physical qubit count would reach approximately 196 for 18 logical qubits, or roughly 10.9 physical qubits per logical qubit. Infleqtion has not published a total-qubit figure; its blog says the syndrome ancillas are not counted in the 18/98 ratio. A distance-3 surface code uses 17 total physical qubits (9 data plus 8 ancilla) for one logical qubit. On this total-physical-qubit estimate, the HGPS code’s advantage over a distance-3 surface code is roughly 1.6-fold. Against higher-distance surface codes, the HGPS advantage is larger: at distance 5, a surface code needs 49 total physical qubits per logical qubit, putting the HGPS code’s estimated total overhead at roughly 4.5 times lower. The “up to five times fewer” framing in Infleqtion’s announcement is defensible only against these higher-distance codes, and it counts data qubits alone.

Second, the HGPS code’s distance of 4 limits the number of errors it can correct to one per block – the same floor as a distance-3 surface code. Fault-tolerant computation at scale requires code distances above 4. Surface codes at distance 7, which Google demonstrated on its Willow chip in December 2024 with below-threshold error suppression, offer meaningfully stronger protection. The encoding efficiency of qLDPC codes is their draw, but the protection per logical qubit at this code distance remains thin.

Quantinuum demonstrated concatenated Iceberg codes on its Helios system in November 2025 – later branded Skinny Logic – running 48 error-corrected logical qubits on 98 trapped ions, roughly 2:1. The QuEra-Harvard-MIT collaboration demonstrated a [[16,6,4]] code at roughly 2.7:1 and projected, in simulation, high-rate qLDPC codes that use 2,304 physical qubits to encode 1,156 logical qubits. IBM has pursued bivariate bicycle qLDPC codes encoding 12 logical qubits in one block of 144 data qubits, though the [[144,12,12]] gross code remains a simulation result. Infleqtion’s HGPS code uses 5.4 data qubits per logical qubit: more than the 2.7 of the QuEra-Harvard-MIT code at the same distance of 4, fewer than the 12 of IBM’s distance-12 gross code.

CUDA-Q Logical separates code design from compilation

The more consequential development is NVIDIA’s CUDA-Q Logical itself and the fact that Infleqtion is among the first hardware vendors – and the first disclosed neutral-atom team – to integrate a qLDPC code into it.

Most quantum error correction demonstrations so far have been bespoke efforts – a specific code, hand-compiled for a specific hardware platform, with a decoder built or adapted for the occasion. The result is a field full of impressive one-off demonstrations that cannot be compared on equal terms and cannot be reused. In its technical blog, Infleqtion divides the work between the two tools: the qLDPC library provides the code mathematics, and CUDA-Q Logical, in the blog’s words, supplies “the logical ownership, block allocation, and compilation model.” Most earlier QEC demonstrations did not separate the code designer’s work from the compiler engineer’s.

Fermilab researchers used CUDA-Q Logical to evaluate fault-tolerant algorithms across multiple QEC codes and architectures, cutting the development cycle from five months to three weeks. They saved that time by reusing one compilation pipeline across experiments instead of rebuilding it for each one. Iceberg Quantum’s modelling of a Diraq silicon-spin architecture through the same tool suggests the platform is retargetable across modalities.

NVIDIA is doing with fault-tolerant quantum computing what it did with GPU-accelerated AI: building the middleware layer that becomes standard infrastructure. CUDA-Q already provides the programming model for hybrid quantum-classical workloads. CUDA-Q Logical extends that model into the error-corrected regime. Combined with the NVIDIA Ising model family for AI-assisted decoding and NVQLink for low-latency QPU-to-GPU communication, NVIDIA is assembling a full-stack position in fault-tolerant quantum computing without manufacturing a single qubit.

CUDA-Q Logical accelerates QEC development for hardware companies like Infleqtion. It also means their differentiation increasingly depends on the physical hardware and its native advantages – in Infleqtion’s case, the reconfigurable connectivity of neutral-atom arrays – rather than the software stack above it.

The software-to-hardware gap

Infleqtion’s technical blog lists the next steps: “In coming work, we plan to extend this workflow through physical syndrome extraction, neutral-atom noise modeling, detector generation, and decoder benchmarking.”

Each item on that list is a substantial engineering challenge and a prerequisite for running this code on actual hardware.

Physical syndrome extraction on neutral-atom arrays requires moving atoms to perform the HGPS code’s weight-6 stabilizer measurements – a schedule that must interleave parallel operations without introducing correlated errors. Neutral atoms can be moved within the array, which gives them flexible qubit connectivity. Translating the HGPS code’s algebraic connectivity into a physical measurement schedule with acceptable overhead is an open problem.

Atom loss – where atoms escape their traps, a failure mode specific to neutral-atom hardware – and leakage to unwanted energy levels must be incorporated into the noise model before any decoder can operate meaningfully. In a reconfigurable neutral-atom array, both produce biased, correlated, and position-dependent errors, unlike the depolarising noise channels used in most QEC simulations.

The decoder must then keep pace with the syndrome stream in real time. Quantinuum’s NVQLink demonstration achieved a 67-microsecond median decoding latency for a qLDPC code on its Helios trapped-ion system – roughly 32 times faster than Helios’s real-time decoding requirement. Neutral-atom systems, with their intermediate gate speeds (faster than trapped ions, slower than superconducting transmons), will impose their own decoder timing budget. Whether GPU-accelerated decoding via NVQLink meets that budget under realistic neutral-atom noise conditions is an empirical question that this announcement does not answer.

Infleqtion demonstrated that the qLDPC code and the CUDA-Q Logical compiler work together. The stabilizers commute over GF(2), the logical ports are properly allocated, and the compilation pipeline produces a verified output. Characterising this result as a reduction in physical qubit requirements – which implies hardware performance – stretches what was actually shown.

What to watch

The first is the syndrome extraction schedule for the HGPS code on a reconfigurable neutral-atom array. The weight-6 checks require each ancilla qubit to interact with six data qubits, and the schedule must minimise atom movement while maintaining parallel operations. Infleqtion’s architecture research with Fred Chong’s laboratory at the University of Chicago is aimed squarely at this problem.

The second is decoder performance under neutral-atom noise. The NVIDIA Ising models, which provide AI-assisted decoding, must be trained or tuned on a noise model that reflects atom-loss, leakage, and the spatially varying fidelity of a real array. QEC results on real hardware have historically been worse than simulated noise models predicted.

The third is whether CUDA-Q Logical becomes the standard compilation layer for fault-tolerant quantum computing across the industry. If it does, the value of any individual code integration diminishes – the tool becomes table stakes – and vendors compete on hardware fidelity and scale. If no single compilation layer becomes standard, each vendor’s toolchain remains a silo, and the field’s progress toward fault tolerance slows.

For now, this is a well-executed software integration that validates qLDPC code construction within a general-purpose compiler framework. Infleqtion has compiled and verified the [[98,18,4]] code in CUDA-Q Logical but has not yet run it on neutral-atom hardware.

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