Chip Industry Technical Paper Roundup: Aug. 18

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New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
ReVolt: Power Delivery Network-Aware Voltage Droop Control for 2.5D PIM Chiplet Architectures Washington State University, University of Wisconsin–Madison
SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes NVIDIA, Duke University
Are Gate-All-Around 2D CFETs the Optimal Architecture for the A2 Node and Beyond? imec
From Lithography to Nanoimprint: Physics-Based, Data-Driven, and Hybrid Frameworks for Defect Prediction in Advanced Patterning Technologies National Taiwan University
Innovative FA Hardware Solution to Enable System-Level Debug of 3D ICs Google, Delft University of Technology
FAPlace: Joint Optimization of Chiplet Placement and Interposer Footprint for 2.5D Systems A*STAR
Self-Focusing Control for Depth-Precise Wafer Slicing of 4H-SiC in Femtosecond Laser Processing Texas A&M University, KIMM, UST

Find more semiconductor research papers here.

The post Chip Industry Technical Paper Roundup: Aug. 18 appeared first on Semiconductor Engineering.

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